The present invention relates to a semiconductor device that can control power supply voltage supplied to an internal circuit included therein.
Recent developments of semiconductor integrated circuits use techniques of lowering power supply voltage to reduce power. This is because a dynamic component of power consumption of a semiconductor integrated circuit is in proportion to the square of the power supply voltage. The techniques of lowering the power supply voltage are therefore most effective techniques for reducing the power to the semiconductor integrated circuit.
From such a point of view, a method has recently been proposed which supplies a minimum voltage at all times by controlling the power supply voltage adaptively to operating frequency of the semiconductor integrated circuit, process variations or the like.
FIG. 15 is a block diagram showing a configuration of a conventional semiconductor device. As shown in FIG. 15, the conventional semiconductor device includes: a register 8, a pulse generating circuit 10, a delayed signal generating circuit 11, a delay difference detecting circuit 12, a control circuit 13, a power supply circuit 14, and a target circuit 15.
The pulse generating circuit 10 and the target circuit 15 are supplied with a clock signal Ck. The delayed signal generating circuit 11 is connected to the register 8 and the pulse generating circuit 10. The delay difference detecting circuit 12 is connected to the pulse generating circuit 10 and the delayed signal generating circuit 11. The control circuit 13 is connected to the delay difference detecting circuit 12. The power supply circuit 14 is connected to the control circuit 13. The power supply circuit 14 supplies a power supply voltage VDD to the delayed signal generating circuit 11 and the target circuit 15. Incidentally, the power supply circuit 14 may supply the power supply voltage VDD not only to the target circuit 15 and the delayed signal generating circuit 11 but also to the pulse generating circuit 10, the delay difference detecting circuit 12, and the control circuit 13.
In the semiconductor device having a configuration as described above, the pulse generating circuit 10 is supplied with the clock signal Ck to generate a reference pulse signal S1 and generate a detection pulse signal S3 for detecting an amount of delay of the generated reference signal S1. As shown in FIGS. 16A to 16D, the detection pulse signal S3 is delayed by for example a period from a time T1 to a time T3, that is, one cycle of the clock signal Ck with respect to the reference pulse signal S1.
The reference pulse signal S1 is supplied to the delayed signal generating circuit 11 to be delayed by a delay time DT from the time T1 to a time T2 by a delay component equal to a delay component possessed by the target circuit 15, whereby a delayed pulse signal S2 as shown in FIG. 16C is generated.
The delay difference detecting circuit 12 compares a phase of the thus generated delayed pulse signal S2 with that of the detection pulse signal S3 supplied from the pulse generating circuit 10, to thereby detect a delay difference DD, a period from the time T2 to the time T3 shown in FIG. 16D, and generate a signal S4 corresponding to the delay difference. Then, in response to the signal S4 being supplied to the control circuit 13, the control circuit 13 supplies the power supply circuit 14 with a control signal S5 for reducing the delay difference to zero. Thus, the power supply circuit 14 lowers the power supply voltage VDD until the delay difference DD is reduced to zero, thereby reducing power consumption of the target circuit 15.
FIG. 17 is a diagram showing a configuration of the delayed signal generating circuit 11 shown in FIG. 15. As shown in FIG. 17, the delayed signal generating circuit 11 includes a plurality of buffers 7 connected in series with each other in multiple stages and a selector SE. The selector SE selectively connects either one of nodes between the buffers 7 with an output node in response to a setting signal SS supplied from the register 8, thereby adjusting the number of buffers 7 through which the reference pulse signal S1 supplied to the delayed signal generating circuit 11 propagates. Thus, the same delay characteristic as that of the target circuit 15 is realized. Incidentally, the setting signal SS is stored in advance in the register 8.
However, since the delayed signal generating circuit 11 realizes the desired delay characteristic by the selector SE, as described above, the reference pulse signal 51 is delayed also by the selector SE itself and the like, thus deteriorating accuracy of the delay difference detected by the delay difference detecting circuit 12.
More specifically, an undesired delay component included in a transmission path of the reference pulse signal S1 makes it impossible to control the power supply voltage VDD with high accuracy.
The present invention has been made to solve such problems, and it is accordingly an object of the present invention to provide a semiconductor device capable of controlling the power supply voltage supplied to the internal circuit with high accuracy by realizing the delay characteristic equal to the delay characteristic of a critical path of the internal circuit with high accuracy.
The object of the present invention is achieved by providing a semiconductor device comprising: delay means for delaying an input signal by a delay time caused by a delay component on a critical path of an internal circuit by delay amount selecting means included in the delay means, and thereby generating a delayed signal; reference signal generating means, having a delay component identical with a delay component of the delay amount selecting means, for generating a reference signal delayed in phase by one cycle of an internal operating clock signal in comparison with the input signal; phase difference detecting means for detecting a phase difference between the reference signal and the delayed signal; and power supply voltage adjusting means for adjusting magnitude of a power supply voltage supplied to the internal circuit according to the phase difference detected by the phase difference detecting means.
The xe2x80x9ccritical pathxe2x80x9d mentioned above refers to a transmission path of a maximum signal propagation delay time among signal transmission paths possessed by the internal circuit.
With such means, a delay time caused by the delay amount selecting means itself included in the delay means is cancelled out by the reference signal generating means. Therefore, the delay characteristic possessed by the critical path of the internal circuit can be reproduced with high accuracy. It is thus possible to improve accuracy in adjustment of the power supply voltage by the power supply voltage adjusting means.
The delay means can delay the input signal by any one of a gate, wiring, capacitor, and a MOS transistor, for example.
Moreover, when the wiring is formed by connecting a plurality of wiring layers forming the internal circuit according to a component ratio of the plurality of wiring layers, the delay characteristic possessed by the critical path of the internal circuit can be reproduced with higher accuracy.
In addition, by making a difference between the delay components of the delay means and the reference signal generating means the delay component of an element forming the critical path of the internal circuit, input characteristics such as input capacitance of the delay means and the reference signal generating means can be made substantially the same. It is thus possible to produce the delay characteristic desired with higher accuracy.
Furthermore, the object of the present invention is achieved by providing a semiconductor device comprising: first delay means for delaying an input signal by a first delay time caused by a first delay component on a critical path of an internal circuit by the first delay component with first delay amount selecting means included in the first delay means, and thereby generating a first delayed signal; second delay means for delaying the first delayed signal by a second delay time caused by a second delay component on the critical path of the internal circuit by the second delay component with second delay amount selecting means included in the second delay means, and thereby generating a second delayed signal; reference signal generating means, having a delay component identical with delay components of the first delay amount selecting means and the second delay amount selecting means, for generating a reference signal delayed in phase by one cycle of an internal operating clock signal in comparison with the input signal; phase difference detecting means for detecting a phase difference between the reference signal and the second delayed signal; and power supply voltage adjusting means for adjusting magnitude of a power supply voltage supplied to the internal circuit according to the phase difference detected by the phase difference detecting adjust the different delay components in parallel by means.
With such means, it is possible to arbitrarily adjust the different delay components in parallel by switching the first delay amount selecting means and the second delay amount selecting means. Therefore, accuracy and versatility in adjusting the power supply voltage to the internal circuit can be increased.
Supposing that the first delay component is a delay component of a wiring having a first length and the second delay component is a delay component of a wiring having a second length longer than the first length, it is possible to first roughly adjust the delay time of the input signal by switching the second delay amount selecting means and then finely adjust the delay time by switching the first delay amount selecting means. Therefore, the delay time of the input signal can be adjusted hierarchically with high accuracy.
Furthermore, when a plurality of delay means having different delay components as described above are connected in series with each other, more complex delay characteristics of the internal circuit can be reproduced, so that accuracy and versatility in adjusting the power supply voltage to the internal circuit can be further increased.